What Is AI Inference?

At its core, AI inference refers to using a pre-trained model to perform forward-pass computations on new, previously unseen data in order to generate prediction results. This process can be analyzed in depth from several key perspctives:

Fundamental Differences in Computation Patterns

Unlike training, which requires extensive backpropagation and gradient calculations (often involving high-precision formats such as FP32, FP64, or mixed precision), inference focuses exclusively on forward propagation. This leads to several important characteristics:

• The computation graph is fixed
• Data flows in a single direction
• The execution path is fully known in advance

These properties allow hardware to be optimized to an extreme degree, for example:

Operator Fusion

Multiple consecutive neural network layers (such as Conv–BN–ReLU) can be fused into a single, highly optimized kernel, significantly reducing off-chip memory accesses. Since memory access is one of the primary bottlenecks for inference latency and power consumption, operator fusion delivers substantial performance and efficiency gains.

Static Scheduling

Because the computation graph is known before deployment, the compiler can predefine the optimal execution schedule, eliminating runtime dynamic scheduling overhead entirely.

Reduced Precision Requirements

Training requires high numerical precision to ensure the stability and correctness of gradient descent. Inference, by contrast, is far more tolerant of lower precision. As a result, INT8, INT4, and even binary or ternary networks are widely adopted in inference workloads.

Lower precision delivers two major advantages:

• Compute Throughput Multiplication On the same hardware, INT8 throughput (TOPS) is typically 2× that of FP16 and 4× that of FP32.
• Dramatically Reduced Memory Bandwidth Pressure Weights and activations require far less data movement, meaning memory bandwidth is no longer a severe bottleneck, allowing compute units to be fed more efficiently.
• High throughput, moderate latency
• Handles massive request volumes from thousands or millions of users
• Batch processing is critical to improving utilization

Diversity of Inference Workloads

Cloud Inference

Chip design priorities: compute density and interconnect bandwidth

Edge Inference

• Ultra-low latency and low power consumption
• Real-time processing on cameras, smartphones, vehicles, and IoT devices
• Extremely high demands on energy efficiency

Chip design priorities: power efficiency and on-chip memory capacity

AI Chip Classification

Classification by Use Case

From an application perspective, AI chips can be broadly divided into two categories:

• AI training chips
• AI inference chips

Classification by Architecture

From an architectural perspective, AI chips can also be divided into:

• GPU
• ASIC

(For a detailed comparison, see my previous article “A Comparison of GPU and ASIC Strengths and Weaknesses in AI”.)

Classification by Compute Architecture

Beyond use case (training vs. inference) and chip type (GPU vs. ASIC), AI chips can also be classified by their compute architecture:

SIMT Architecture

Represented by NVIDIA GPUs, SIMT (Single Instruction, Multiple Threads) architectures excel at highly parallel, homogeneous workloads. Their strong programmability and general-purpose flexibility form the foundation of their dominance in AI training.

DSA Architecture

Represented by Google TPU, Domain-Specific Architectures customize hardware units for specific computation patterns such as matrix multiplication and convolution. While extremely efficient, they are less flexible than GPUs.

Dataflow Architecture

Represented by Graphcore IPU, dataflow architectures map the entire computation graph onto the chip, allowing data to flow directly between processing elements. This greatly reduces global memory access and is especially well suited for graph-based models.

AI Training Chips

The AI Training Market

The AI training chip market has very few serious competitors. NVIDIA alone holds over 90% market share, with its Blackwell architecture supporting training of models with up to 1.8 trillion parameters, and NVLink 6 enabling seamless interconnection of 72-GPU clusters.

Huawei and AMD are the only vendors besides NVIDIA with a meaningful presence in the AI training market. However, their market share exists on a completely different scale and is not directly comparable.

Intel’s Gaudi series has almost no visibility in the market, with a share of less than 1%.

AMD

The MI300X is close to—or even exceeds—the H100 in certain hardware metrics, but the ROCm software ecosystem remains its most significant weakness.

Huawei

The Ascend 910, paired with the CANN software stack, has formed a viable alternative in the domestic Chinese market under policy support. However, it faces challenges globally in terms of software ecosystem maturity and access to advanced manufacturing nodes.

Intel

Gaudi 3 emphasizes cost-effectiveness, but still lags behind leading players in absolute performance and ecosystem maturity.

AI Inference Chips Are Primarily ASICs

AI inference inherently involves vendor-specific algorithms, making customization essential. Customized chips are, by definition, ASICs, which is why AI inference chips are predominantly ASIC-based.

The AI Inference Chip Market

According to Verified Market Research, the global AI inference chip market was valued at USD 15.8 billion in 2023 and is expected to reach USD 90.6 billion by 2030, with a compound annual growth rate (CAGR) of 22.6% from 2024 to 2030.

Key Advantages of ASICs

Ideal for Inference

As discussed earlier, AI inference requires customization to fully exploit each vendor’s proprietary algorithms and unique functional requirements. Only ASICs can deliver this level of specialization.

This explains why, beyond purchasing large volumes of general-purpose GPUs, major companies still invest in developing their own inference ASICs to achieve the exact inference capabilities they need.

Eliminating Flexibility to Maximize Speed

“Fixed-functionality” is the core advantage of ASICs. By tailoring the hardware architecture to a single task, inference logic and data paths can be permanently embedded into the chip.

All unnecessary general-purpose components—such as dynamic scheduling units and generic memory controllers found in GPUs—are removed, allowing 100% of hardware resources to serve inference workloads.

Cost Efficiency

Inference workloads are far more sensitive to energy efficiency (performance per watt) and cost than training workloads, and ASICs offer overwhelming advantages in both areas.

• In terms of energy efficiency, Google TPU v5e delivers 3× the efficiency of NVIDIA H100.
• In terms of cost, AWS Trainium 2 offers 30–40% better price-performance for inference tasks than H100. The unit compute cost of TPU v5 and Trainium 2 is approximately 70% and 60%, respectively, of NVIDIA H100.

A large model may require only tens to hundreds of training chips, but inference at scale can demand tens or even hundreds of thousands of chips. For example, ChatGPT’s inference cluster is more than 10× larger than its training cluster. This makes ASIC customization highly effective at reducing per-chip cost.

Key Disadvantages of ASICs

Long Design Cycles

ASIC design cycles typically span 1–2 years, while AI models evolve at an extremely rapid pace. For example, large language models progressed from GPT-3 to GPT-4 in just one year.

If an ASIC is designed around a model architecture that becomes obsolete (such as CNNs being displaced by Transformers), the chip may effectively become unusable.

Poor Suitability for Training

For the same reasons, ASICs are relatively weak for training workloads. Training requires flexibility and rapid algorithm iteration, and using ASICs for training introduces a high risk of obsolescence, resulting in poor cost-effectiveness.

Major Inference Chips on the Market

Which Major Companies Have Developed Inference Chips?

Virtually every major global technology company you are familiar with—including Apple, Amazon, Google, Meta, Microsoft, Huawei, Tencent, ByteDance, Alibaba, and OpenAI—has already deployed, is deploying, or has commissioned the development of inference chips.

Mostly Outsourced Design

Most AI giants are software companies and do not maintain large internal chip design teams. As a result, ASIC design is typically outsourced.

Currently, Broadcom leads the ASIC market with 55%–60% share, followed by Marvell with 13%–15% share.

Deployed Inference Chips

Below is a list of well-known inference chips that have already been deployed (excluding those still under development):

Company	Representative Products	Architecture	Application Scenarios
Google	TPU v6 series	ASIC	Cloud inference, training
Amazon	Inferentia, Trainium	ASIC	Inferentia for inference, Trainium for training
Microsoft	Maia 100 series	ASIC	Cloud inference, training
Meta	MTIA series	ASIC	Cloud inference, training
Huawei HiSilicon	Ascend 910 series	ASIC	Cloud inference, training
Cambricon	Siyuan 590 series	ASIC	Cloud inference, training
Other vendors	—	—	—

Please note that NVIDIA, AMD, and Intel AI chips can also be used for inference, but their strengths are far more pronounced in training scenarios.

In addition, several smaller startups—such as SambaNova, Cerebras Systems, Graphcore, Groq, Tenstorrent, Hailo, Mythic, and KAIST’s C-Transformer—have introduced AI chips capable of inference. However, shipment volumes remain relatively small and are not comparable to inference chips designed in-house by major technology companies.

Oldal: The Difference Between AI Inference Chips and AI Training Chips
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